PIC18F13K50-I/P【PDF 115/285 页】IC PIC MCU FLASH 4KX16 20-PDIP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3873

111页 112页 113页 114页 [115页]116页 117页 118页 119页

dsPIC30F1010/202X

DS70178C-page 200

Preliminary

2006 Microchip Technology Inc.

bit 5

LOCK: PLL Lock Status bit (read-only)

= Indicates that PLL is in lock

= Indicates that PLL is out of lock (or disabled)

This bit is Reset upon:

Reset on POR

Reset when a valid clock switching sequence is initiated by the clock switch state machine

Set when PLL lock is achieved after a PLL start

Reset when lock is lost

Read zero when PLL is not selected as a Group 1 system clock

bit 4

PRCDEN: Pseudo Random Clock Dither Enable bit

= Pseudo random clock dither is enabled

= Pseudo random clock dither is disabled

bit 3

CF: Clock Fail Detect bit (read/clearable by application)

= FSCM has detected clock failure

= FSCM has NOT detected clock failure

This bit is Reset upon:

Reset on POR

Reset when a valid clock switching sequence is initiated by the clock switch state machine

Set when clock fail detected

bit 2

TSEQEN: FRC Tune Sequencer Enable bit

= The TUN<3:0>, TSEQ1<3:0>,

... , TSEQ7<3:0> bits in the OSCTUN and the OSCTUN2 regis-

ters sequentially tune the FRC oscillator. Each field being sequentially selected via the

ROLL<2:0> signals from the PWM module.

= The TUN<3:0> bits in OSCTUN register tunes the FRC oscillator

bit 1

Unimplemented: Read as ‘0’

bit 0

OSWEN: Oscillator Switch Enable bit

= Request oscillator switch to selection specified by NOSC<1:0> bits

= Oscillator switch is complete

This bit is Reset upon:

Reset on POR

Reset after a successful clock switch

Reset after a redundant clock switch

Reset after FSCM switches the oscillator to (Group 3) FRC

REGISTER 18-1:

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式